Comments on 'Random Serial Bit Code Generator'
If the timing criteria of a flip-flop are violated because data are applied asynchronously with the clock the resulting states of the flip-flop are uncertain; a method that overcomes this problem is suggested.
In the circuit ('Random serial bit rate generator', M. O'Hara, Electronic Product Design, March 1994) the waveform presented to the D input of the flip-flop is asynchronous with the clock and consequently either the minimum set-up (tsu) or the hold (th) times of the flip-flop may not be observed. This failure can result in one of three outcomes: 1/ notwithstanding the timing violations the flip-flop changes state, 2/ the flip- flop remains in its previous state, or 3/ the flip-flop enters a metastable (ms) state where the output changes towards the other state (but does not necessarily enter that state) for an indefinite period before returning to its previous state. The existence of the third possibility often results in improper operation of part of the circuitry. This problem is commonly encountered when interfacing two digital systems that are running asynchronously.
The presence of the ms state is often difficult to determine - it is usually of very short duration and may be quite rare, so it may be easily overlooked if using a low bandwidth or analogue oscilloscope. Increasing the clock frequency will usually increase the frequency of occurrence of the ms state so a digital system whose misbehaviour increases with clock frequency may be suspected of this design fault if the other factors are also present. The applications suggested by M. O'Hara require the average number of changes at the D input to be very much greater than one per clock period (so that adjacent bits in the output are effectively independent) and this may give rise to a significant rate of ms states at the flip-flop output.
The situation can be improved by selecting flip-flops with small total tsu and th but a better solution is to use two flip- flops simultaneously clocked (see figure); if FF1 enters a ms state this is not transferred to FF2 provided that the ms state lasts for less than one clock period. If the ms state persists for longer (because, for example, a short clock period is used) then using gates to delay the clock to FF2 will improve matters provided that the minimum hold time of FF2 is not violated.
Notes
- This article was first published in Electronic Product Design, vol 15, Issue 6; June 1994.